Opcodes

Not a lot of work done today on the project, due to Paul Ayres popping over last night and making us drink lots of alcohol. Anyway, this afternoon I did some thinking whilst sitting on the bench by the herb garden.

The decision to go for a 16-bit word size allows a lot of space when designing the opcodes, which in turn should make life less complicated when designing the decode circuits.

I have to say that I'm finding it difficult to put out of my mind the actual building of the machine, but I will keep telling myself that you can't order any parts until the design is 100% complete. I still have lots of bits left over from the "Build an Electric Guitar from scratch" project, so I'm trying to be good this time.

Anyway, we have 8-bits of MSB for the instruction root opcode, and 8-bits of LSB for the instruction variant opcode. When I say root I mean the general class of instruction, e.g. ADD, ADC and INC are the same instruction (same root) just with slight variants.

I think that I'll be totally random and assign the MSB of the opcode on the basis of the alphabetical order of the mnemonics of the root opcodes. Hell, it is nice to bolt down some part of the design. Already changed my mind, I won't do that exactly.

So let us group the roots!

ADD -->

ADC
ADD
INC

LOGICAL -->

AND
OR
XOR
CPL
NEG
XB

SUBTRACT -->

CP
DEC
SBC
SUB

DEBUG -->

HALT
NOP

MEMORY/I-O -->

IN
LD
OUT

BRANCH -->

JP CC
JP NNNN

Looking at the above groupings make me wonder why we have separate IN and OUT instructions, after all LD is used for both getting and storing items from memory. Why not just have IO as a single instruction? Like the idea and that is what we will do.

So that group becomes:

MEMORY/I-O -->

IO
LD

The "Logical" group really is a group of roots, i.e. they are not related, other than by being logical. For now will keep them together, but I don't rule out splitting them apart in the future.