Specifications

Well now, what is needed and what is nice to have?

A fair question which has been troubling by mind these past few days.

When I was at college I was a big fan of the DEC PDP-11, mainly because it was hidden in a room that not many people seemed to know about. Consequently it ran my stuff really quickly compared to the Honeywell time sharing system that everyone else used.

Anyway, memory lane aside, the task is to design and build a 1970s mini-computer from scratch.

Looking up on the web it seems like the PDP-11 moved to using microprocessors around 1977/8, prior to that it had been using MSI chips. So I think that specification wise I'll go for an early 1970s PDP-11, but not a PDP-11. The word size will however be 16 bits.

Early PDP-11s only had about 8k of memory. That seems a little small so let us have lots of memory, ... 64k. The address bus width will therefore be 16 bits as well. This will make address calculation easier in the long run (I hope). Extra memory can be added if needed in the future by paging, or increasing the address bus width. Remember UNIX ran on the PDP-11s predecessor with far less memory, so 64k is luxury.

I/O ports will be memory mapped (i.e. use the same address bus as memory), however it will be a different space than for RAM and ROM, effectively paged.

In summary data bus width 16-bits, address bus width 16 bits; the buses are shared by the memory (RAM/ROM) and the i/o port spaces.

Registers:

Accumulator - 16 bit - YES
Program Counter - 16 bit - YES
Stack Pointer - 16 bit - NO
Address Register - 16 bit - YES (like HL register in the 8080/Z80) (maybe internal to CPU only)
Instruction Register - 16 bit (internal to CPU only)
Data Register - 16 bit (internal to CPU only)
Refresh Register - 16 bit - NO (not yet)
Flag Register - 16 bit

The reason I've decided not to have a Stack Pointer, and hence the ability to implement subroutine calls and interrupt handlers, is that the IPS operating system doesn't use them and so adding the feature just adds complexity, and that is what we do not want. IPS is a stack based language, but it doesn't need a hardware stack implementation.

The Refresh Register is not required as I've decided to use static RAM only, instead of dynamic RAM. Static RAM is so cheap these days and does not need refreshing like dynamic RAM (back in the 1970s it was very expensive and had slow access times).

The Flag Register is set at 16-bits, although far fewer bits are actually required. It is 16-bit just to keep the design flat, i.e. the same across all registers, and to leave room for extension in the future.

The Flag bits decided upon so far are:

S - Sign (MSB of result)
Z - Zero (1 if result zero, 0 otherwise)
C - Carry (1 if the operation produced a carry from the MSB of the operand or result)
E - External Flag (used for the IPS 20ms pseudo-interrupt)

Opcodes:

So what instructions shall I implement?

The key driver here is what do we need to implement IPS. If it is not necessary for IPS we won't include it (yet).

This is the first cut. What I've done is gone through my old copy of the Z80 programming Manual and picked out the "need to have" instructions. I'm sure that some will be added and/or dropped in the future, but we have to start somewhere. I should note that I haven't decided upon operands yet, only that one of them will be the Accumulator.

ADC - Add with carry
ADD - Add without carry
AND - Logical AND
CP - Compare (maybe)
CPL - Inverted 1's complement (maybe)
DEC - Decrement by 1
HALT - Stops the CPU (maybe)
IN - Read from I/O port
INC - Increment by 1
JP CC - Jump to address conditional
JP nnnn Jump to address
LD - Load (and store)
NEG - Negated 2's complement (maybe)
NOP - No operation
OR - Logical OR
OUT - Output to I/O port
SBC - Subtract with carry (borrow)
SUB - Subtract without carry (borrow)
XOR - Logical exclusive OR

There are quite a few "maybe" instructions above, time will tell how things turn out. Notable omissions are the calls/returns, and the rotate/shift instructions.