Reviewing the situation

I've been reading the PDP-11 manual mentioned earlier. It is so cool, I can see why the PDP-11 was in production for 20+ years.

Anyway, I'm not going to build a PDP-11, just a machine that internally is very similar.

Registers:

R0
R1
R2
R3
R4
R5
R6 (Stack Pointer)
R7 (Program Counter)

Instructions (the numeric values of the opcodes below are in octal):

00 00 00 HALT
00 00 05 RESET
00 01 DD JMP
00 02 0R RTS
00 02 40 NOP
00 03 DD SWAB
00 04 XXX BR
00 10 XXX BNE
00 14 XXX BEQ
00 20 XXX BGE
00 24 XXX BLT
00 30 XXX BGT
00 34 XXX BLE
00 4R DD JSR
00 50 DD CLR
00 51 DD COM
00 52 DD INC
00 53 DD DEC
00 54 DD NEG
00 55 DD ADC
00 56 DD SBC
00 57 DD TST
00 60 DD ROR
00 61 DD ROL
00 62 DD ASR
00 63 DD ASL
00 67 DD SXT
01 SS DD MOV
02 SS DD CMP
03 SS DD BIT
04 SS DD BIC
05 SS DD BIS
06 SS DD ADD
07 4R DD XOR
07 7R NN SOB
10 00 XXX BPL
10 04 XXX BMI
10 10 XXX BHI
10 14 XXX BLOS
10 20 XXX BVC
10 24 XXX BVS
10 30 XXX BCC, BHIS
10 34 XXX BCS, BLO
10 50 DD CLRB
10 51 DD COMB
10 52 DD INCB
10 53 DD DECB
10 54 DD NEGB
10 55 DD ADCB
10 56 DD SBCB
10 57 DD TSTB
10 60 DD RORB
10 61 DD ROLB
10 62 DD ASRB
10 63 DD ASLB
11 SS DD MOVB
12 SS DD CMPB
13 SS DD BITB
14 SS DD BICB
15 SS DD BISB
16 SS DD SUB

In the above:

DD means destination field (6 bits)
SS means source field (6 bits)
XXX means an offset (8 bits), +127, -128
N means a number (3 bits)
NN means a number (6 bits)
R means general register (3 bits), 0, 7

I've decided for the time being to not implement the PDP-11 traps, interrupts, and modes (user/kernel).

In an earlier post I had decided to have separate memory and i/o spaces sharing the same address bus. I have now changed my mind, we will have all i/o mapped into the memory space as per the PDP-11.

The External Flag (used for the 20ms IPS pseudo-interrupt) will now be memory mapped instead of being a bit in the Processor Status Word (PSW) aka Flags Register. The PSW is rather empty:

Bit 0 - C (Carry)
Bit 1 - V (Overflow)
Bit 2 - Z (Zero)
Bit 3 - N (Negative)
Bits 4-15 Reserved